mirror of
https://github.com/edera-dev/krata.git
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feat: pci passthrough (#114)
* feat: pci passthrough * feat: guest device management * feat: addons mounting and kernel modules support * feat: more pci work * fix: kernel build squashfs fixes * fix: e820entry should be available on all platforms
This commit is contained in:
Alex Zenla
GitHub
@ -3,23 +3,29 @@ pub mod sys;
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use crate::error::{Error, Result};
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use crate::sys::{
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AddressSize, CreateDomain, DomCtl, DomCtlValue, DomCtlVcpuContext, EvtChnAllocUnbound,
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GetDomainInfo, GetPageFrameInfo3, Hypercall, HypercallInit, MaxMem, MaxVcpus, MemoryMap,
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MemoryReservation, MmapBatch, MmapResource, MmuExtOp, MultiCallEntry, VcpuGuestContext,
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VcpuGuestContextAny, XenCapabilitiesInfo, HYPERVISOR_DOMCTL, HYPERVISOR_EVENT_CHANNEL_OP,
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HYPERVISOR_MEMORY_OP, HYPERVISOR_MMUEXT_OP, HYPERVISOR_MULTICALL, HYPERVISOR_XEN_VERSION,
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XENVER_CAPABILITIES, XEN_DOMCTL_CREATEDOMAIN, XEN_DOMCTL_DESTROYDOMAIN,
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XEN_DOMCTL_GETDOMAININFO, XEN_DOMCTL_GETPAGEFRAMEINFO3, XEN_DOMCTL_GETVCPUCONTEXT,
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XEN_DOMCTL_HYPERCALL_INIT, XEN_DOMCTL_MAX_MEM, XEN_DOMCTL_MAX_VCPUS, XEN_DOMCTL_PAUSEDOMAIN,
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XEN_DOMCTL_SETVCPUCONTEXT, XEN_DOMCTL_SET_ADDRESS_SIZE, XEN_DOMCTL_UNPAUSEDOMAIN,
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XEN_MEM_CLAIM_PAGES, XEN_MEM_MEMORY_MAP, XEN_MEM_POPULATE_PHYSMAP,
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AddressSize, AssignDevice, CreateDomain, DomCtl, DomCtlValue, DomCtlVcpuContext,
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EvtChnAllocUnbound, GetDomainInfo, GetPageFrameInfo3, Hypercall, HypercallInit,
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IoMemPermission, IoPortPermission, IrqPermission, MaxMem, MaxVcpus, MemoryMap,
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MemoryReservation, MmapBatch, MmapResource, MmuExtOp, MultiCallEntry, PciAssignDevice,
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VcpuGuestContext, VcpuGuestContextAny, XenCapabilitiesInfo, DOMCTL_DEV_PCI, HYPERVISOR_DOMCTL,
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HYPERVISOR_EVENT_CHANNEL_OP, HYPERVISOR_MEMORY_OP, HYPERVISOR_MMUEXT_OP, HYPERVISOR_MULTICALL,
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HYPERVISOR_XEN_VERSION, XENVER_CAPABILITIES, XEN_DOMCTL_ASSIGN_DEVICE, XEN_DOMCTL_CREATEDOMAIN,
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XEN_DOMCTL_DESTROYDOMAIN, XEN_DOMCTL_GETDOMAININFO, XEN_DOMCTL_GETPAGEFRAMEINFO3,
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XEN_DOMCTL_GETVCPUCONTEXT, XEN_DOMCTL_HYPERCALL_INIT, XEN_DOMCTL_IOMEM_PERMISSION,
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XEN_DOMCTL_IOPORT_PERMISSION, XEN_DOMCTL_IRQ_PERMISSION, XEN_DOMCTL_MAX_MEM,
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XEN_DOMCTL_MAX_VCPUS, XEN_DOMCTL_PAUSEDOMAIN, XEN_DOMCTL_SETVCPUCONTEXT,
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XEN_DOMCTL_SET_ADDRESS_SIZE, XEN_DOMCTL_UNPAUSEDOMAIN, XEN_MEM_CLAIM_PAGES, XEN_MEM_MEMORY_MAP,
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XEN_MEM_POPULATE_PHYSMAP,
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};
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use libc::{c_int, mmap, usleep, MAP_FAILED, MAP_SHARED, PROT_READ, PROT_WRITE};
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use log::trace;
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use nix::errno::Errno;
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use std::ffi::{c_long, c_uint, c_ulong, c_void};
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use std::sync::Arc;
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use sys::{XEN_DOMCTL_MAX_INTERFACE_VERSION, XEN_DOMCTL_MIN_INTERFACE_VERSION};
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use sys::{
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E820Entry, ForeignMemoryMap, PhysdevMapPirq, HYPERVISOR_PHYSDEV_OP, PHYSDEVOP_MAP_PIRQ,
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XEN_DOMCTL_MAX_INTERFACE_VERSION, XEN_DOMCTL_MIN_INTERFACE_VERSION, XEN_MEM_SET_MEMORY_MAP,
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};
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use tokio::sync::Semaphore;
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use std::fs::{File, OpenOptions};
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@ -569,26 +575,42 @@ impl XenCall {
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Ok(())
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}
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pub async fn get_memory_map(&self, size_of_entry: usize) -> Result<Vec<u8>> {
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pub async fn get_memory_map(&self, max_entries: u32) -> Result<Vec<E820Entry>> {
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let mut memory_map = MemoryMap {
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count: 0,
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count: max_entries,
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buffer: 0,
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};
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let mut entries = vec![E820Entry::default(); max_entries as usize];
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memory_map.buffer = entries.as_mut_ptr() as c_ulong;
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self.hypercall2(
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HYPERVISOR_MEMORY_OP,
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XEN_MEM_MEMORY_MAP as c_ulong,
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addr_of_mut!(memory_map) as c_ulong,
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)
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.await?;
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entries.truncate(memory_map.count as usize);
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Ok(entries)
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}
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pub async fn set_memory_map(
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&self,
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domid: u32,
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entries: Vec<E820Entry>,
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) -> Result<Vec<E820Entry>> {
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let mut memory_map = ForeignMemoryMap {
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domid: domid as u16,
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map: MemoryMap {
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count: entries.len() as u32,
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buffer: entries.as_ptr() as u64,
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},
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};
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self.hypercall2(
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HYPERVISOR_MEMORY_OP,
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XEN_MEM_MEMORY_MAP as c_ulong,
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XEN_MEM_SET_MEMORY_MAP as c_ulong,
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addr_of_mut!(memory_map) as c_ulong,
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)
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.await?;
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let mut buffer = vec![0u8; memory_map.count as usize * size_of_entry];
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memory_map.buffer = buffer.as_mut_ptr() as c_ulong;
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self.hypercall2(
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HYPERVISOR_MEMORY_OP,
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XEN_MEM_MEMORY_MAP as c_ulong,
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addr_of_mut!(memory_map) as c_ulong,
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)
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.await?;
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Ok(buffer)
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Ok(entries)
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}
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pub async fn populate_physmap(
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@ -671,4 +693,140 @@ impl XenCall {
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.await
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.map(|_| ())
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}
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pub async fn iomem_permission(
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&self,
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domid: u32,
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first_mfn: u64,
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nr_mfns: u64,
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allow: bool,
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) -> Result<()> {
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trace!(
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"domctl fd={} iomem_permission domid={} first_mfn={:#x}, nr_mfns={:#x} allow={}",
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self.handle.as_raw_fd(),
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domid,
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first_mfn,
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nr_mfns,
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allow,
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);
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let mut domctl = DomCtl {
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cmd: XEN_DOMCTL_IOMEM_PERMISSION,
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interface_version: self.domctl_interface_version,
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domid,
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value: DomCtlValue {
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iomem_permission: IoMemPermission {
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first_mfn,
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nr_mfns,
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allow: if allow { 1 } else { 0 },
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},
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},
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};
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self.hypercall1(HYPERVISOR_DOMCTL, addr_of_mut!(domctl) as c_ulong)
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.await?;
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Ok(())
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}
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pub async fn ioport_permission(
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&self,
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domid: u32,
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first_port: u32,
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nr_ports: u32,
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allow: bool,
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) -> Result<()> {
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trace!(
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"domctl fd={} ioport_permission domid={} first_port={:#x}, nr_ports={:#x} allow={}",
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self.handle.as_raw_fd(),
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domid,
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first_port,
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nr_ports,
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allow,
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);
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let mut domctl = DomCtl {
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cmd: XEN_DOMCTL_IOPORT_PERMISSION,
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interface_version: self.domctl_interface_version,
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domid,
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value: DomCtlValue {
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ioport_permission: IoPortPermission {
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first_port,
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nr_ports,
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allow: if allow { 1 } else { 0 },
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},
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},
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};
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self.hypercall1(HYPERVISOR_DOMCTL, addr_of_mut!(domctl) as c_ulong)
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.await?;
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Ok(())
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}
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pub async fn irq_permission(&self, domid: u32, irq: u32, allow: bool) -> Result<()> {
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trace!(
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"domctl fd={} irq_permission domid={} irq={} allow={}",
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self.handle.as_raw_fd(),
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domid,
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irq,
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allow,
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);
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let mut domctl = DomCtl {
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cmd: XEN_DOMCTL_IRQ_PERMISSION,
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interface_version: self.domctl_interface_version,
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domid,
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value: DomCtlValue {
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irq_permission: IrqPermission {
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pirq: irq,
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allow: if allow { 1 } else { 0 },
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pad: [0; 3],
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},
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},
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};
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self.hypercall1(HYPERVISOR_DOMCTL, addr_of_mut!(domctl) as c_ulong)
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.await?;
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Ok(())
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}
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pub async fn map_pirq(&self, domid: u32, index: isize, pirq: Option<u32>) -> Result<u32> {
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trace!(
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"physdev fd={} map_pirq domid={} index={} pirq={:?}",
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self.handle.as_raw_fd(),
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domid,
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index,
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pirq,
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);
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let mut physdev = PhysdevMapPirq::default();
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physdev.domid = domid as u16;
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physdev.typ = 0x1;
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physdev.index = index as c_int;
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physdev.pirq = pirq.map(|x| x as c_int).unwrap_or(index as c_int);
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self.hypercall2(
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HYPERVISOR_PHYSDEV_OP,
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PHYSDEVOP_MAP_PIRQ,
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addr_of_mut!(physdev) as c_ulong,
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)
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.await?;
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Ok(physdev.pirq as u32)
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}
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pub async fn assign_device(&self, domid: u32, sbdf: u32, flags: u32) -> Result<()> {
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trace!(
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"domctl fd={} assign_device domid={} sbdf={} flags={}",
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self.handle.as_raw_fd(),
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domid,
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sbdf,
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flags,
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);
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let mut domctl = DomCtl {
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cmd: XEN_DOMCTL_ASSIGN_DEVICE,
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interface_version: self.domctl_interface_version,
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domid,
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value: DomCtlValue {
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assign_device: AssignDevice {
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device: DOMCTL_DEV_PCI,
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flags,
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pci_assign_device: PciAssignDevice { sbdf, padding: 0 },
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},
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},
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};
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self.hypercall1(HYPERVISOR_DOMCTL, addr_of_mut!(domctl) as c_ulong)
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.await?;
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Ok(())
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}
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}
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