mirror of
https://github.com/edera-dev/krata.git
synced 2025-08-03 05:10:55 +00:00
feat: more pci work
This commit is contained in:
Alex Zenla
parent
5dea89f644
commit
97c4880605
@ -3,15 +3,17 @@ pub mod sys;
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use crate::error::{Error, Result};
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use crate::sys::{
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AddressSize, CreateDomain, DomCtl, DomCtlValue, DomCtlVcpuContext, EvtChnAllocUnbound,
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GetDomainInfo, GetPageFrameInfo3, Hypercall, HypercallInit, IoMemPermission, IoPortPermission,
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MaxMem, MaxVcpus, MemoryMap, MemoryReservation, MmapBatch, MmapResource, MmuExtOp,
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MultiCallEntry, VcpuGuestContext, VcpuGuestContextAny, XenCapabilitiesInfo, HYPERVISOR_DOMCTL,
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AddressSize, AssignDevice, CreateDomain, DomCtl, DomCtlValue, DomCtlVcpuContext,
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EvtChnAllocUnbound, GetDomainInfo, GetPageFrameInfo3, Hypercall, HypercallInit,
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IoMemPermission, IoPortPermission, IrqPermission, MaxMem, MaxVcpus, MemoryMap,
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MemoryReservation, MmapBatch, MmapResource, MmuExtOp, MultiCallEntry, PciAssignDevice,
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VcpuGuestContext, VcpuGuestContextAny, XenCapabilitiesInfo, DOMCTL_DEV_PCI, HYPERVISOR_DOMCTL,
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HYPERVISOR_EVENT_CHANNEL_OP, HYPERVISOR_MEMORY_OP, HYPERVISOR_MMUEXT_OP, HYPERVISOR_MULTICALL,
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HYPERVISOR_XEN_VERSION, XENVER_CAPABILITIES, XEN_DOMCTL_CREATEDOMAIN, XEN_DOMCTL_DESTROYDOMAIN,
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XEN_DOMCTL_GETDOMAININFO, XEN_DOMCTL_GETPAGEFRAMEINFO3, XEN_DOMCTL_GETVCPUCONTEXT,
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XEN_DOMCTL_HYPERCALL_INIT, XEN_DOMCTL_IOMEM_PERMISSION, XEN_DOMCTL_IOPORT_PERMISSION,
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XEN_DOMCTL_MAX_MEM, XEN_DOMCTL_MAX_VCPUS, XEN_DOMCTL_PAUSEDOMAIN, XEN_DOMCTL_SETVCPUCONTEXT,
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HYPERVISOR_XEN_VERSION, XENVER_CAPABILITIES, XEN_DOMCTL_ASSIGN_DEVICE, XEN_DOMCTL_CREATEDOMAIN,
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XEN_DOMCTL_DESTROYDOMAIN, XEN_DOMCTL_GETDOMAININFO, XEN_DOMCTL_GETPAGEFRAMEINFO3,
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XEN_DOMCTL_GETVCPUCONTEXT, XEN_DOMCTL_HYPERCALL_INIT, XEN_DOMCTL_IOMEM_PERMISSION,
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XEN_DOMCTL_IOPORT_PERMISSION, XEN_DOMCTL_IRQ_PERMISSION, XEN_DOMCTL_MAX_MEM,
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XEN_DOMCTL_MAX_VCPUS, XEN_DOMCTL_PAUSEDOMAIN, XEN_DOMCTL_SETVCPUCONTEXT,
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XEN_DOMCTL_SET_ADDRESS_SIZE, XEN_DOMCTL_UNPAUSEDOMAIN, XEN_MEM_CLAIM_PAGES, XEN_MEM_MEMORY_MAP,
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XEN_MEM_POPULATE_PHYSMAP,
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};
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@ -20,7 +22,10 @@ use log::trace;
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use nix::errno::Errno;
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use std::ffi::{c_long, c_uint, c_ulong, c_void};
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use std::sync::Arc;
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use sys::{XEN_DOMCTL_MAX_INTERFACE_VERSION, XEN_DOMCTL_MIN_INTERFACE_VERSION};
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use sys::{
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E820Entry, ForeignMemoryMap, PhysdevMapPirq, HYPERVISOR_PHYSDEV_OP, PHYSDEVOP_MAP_PIRQ,
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XEN_DOMCTL_MAX_INTERFACE_VERSION, XEN_DOMCTL_MIN_INTERFACE_VERSION, XEN_MEM_SET_MEMORY_MAP,
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};
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use tokio::sync::Semaphore;
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use std::fs::{File, OpenOptions};
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@ -570,26 +575,42 @@ impl XenCall {
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Ok(())
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}
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pub async fn get_memory_map(&self, size_of_entry: usize) -> Result<Vec<u8>> {
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pub async fn get_memory_map(&self, max_entries: u32) -> Result<Vec<E820Entry>> {
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let mut memory_map = MemoryMap {
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count: 0,
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count: max_entries,
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buffer: 0,
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};
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let mut entries = vec![E820Entry::default(); max_entries as usize];
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memory_map.buffer = entries.as_mut_ptr() as c_ulong;
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self.hypercall2(
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HYPERVISOR_MEMORY_OP,
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XEN_MEM_MEMORY_MAP as c_ulong,
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addr_of_mut!(memory_map) as c_ulong,
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)
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.await?;
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entries.truncate(memory_map.count as usize);
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Ok(entries)
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}
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pub async fn set_memory_map(
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&self,
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domid: u32,
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entries: Vec<E820Entry>,
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) -> Result<Vec<E820Entry>> {
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let mut memory_map = ForeignMemoryMap {
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domid: domid as u16,
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map: MemoryMap {
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count: entries.len() as u32,
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buffer: entries.as_ptr() as u64,
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},
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};
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self.hypercall2(
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HYPERVISOR_MEMORY_OP,
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XEN_MEM_MEMORY_MAP as c_ulong,
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XEN_MEM_SET_MEMORY_MAP as c_ulong,
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addr_of_mut!(memory_map) as c_ulong,
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)
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.await?;
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let mut buffer = vec![0u8; memory_map.count as usize * size_of_entry];
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memory_map.buffer = buffer.as_mut_ptr() as c_ulong;
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self.hypercall2(
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HYPERVISOR_MEMORY_OP,
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XEN_MEM_MEMORY_MAP as c_ulong,
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addr_of_mut!(memory_map) as c_ulong,
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)
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.await?;
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Ok(buffer)
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Ok(entries)
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}
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pub async fn populate_physmap(
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@ -736,4 +757,76 @@ impl XenCall {
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.await?;
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Ok(())
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}
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pub async fn irq_permission(&self, domid: u32, irq: u32, allow: bool) -> Result<()> {
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trace!(
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"domctl fd={} irq_permission domid={} irq={} allow={}",
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self.handle.as_raw_fd(),
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domid,
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irq,
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allow,
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);
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let mut domctl = DomCtl {
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cmd: XEN_DOMCTL_IRQ_PERMISSION,
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interface_version: self.domctl_interface_version,
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domid,
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value: DomCtlValue {
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irq_permission: IrqPermission {
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pirq: irq,
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allow: if allow { 1 } else { 0 },
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pad: [0; 3],
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},
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},
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};
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self.hypercall1(HYPERVISOR_DOMCTL, addr_of_mut!(domctl) as c_ulong)
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.await?;
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Ok(())
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}
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pub async fn map_pirq(&self, domid: u32, index: isize, pirq: Option<u32>) -> Result<u32> {
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trace!(
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"physdev fd={} map_pirq domid={} index={} pirq={:?}",
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self.handle.as_raw_fd(),
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domid,
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index,
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pirq,
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);
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let mut physdev = PhysdevMapPirq::default();
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physdev.domid = domid as u16;
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physdev.typ = 0x1;
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physdev.index = index as c_int;
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physdev.pirq = pirq.map(|x| x as c_int).unwrap_or(index as c_int);
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self.hypercall2(
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HYPERVISOR_PHYSDEV_OP,
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PHYSDEVOP_MAP_PIRQ,
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addr_of_mut!(physdev) as c_ulong,
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)
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.await?;
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Ok(physdev.pirq as u32)
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}
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pub async fn assign_device(&self, domid: u32, sbdf: u32, flags: u32) -> Result<()> {
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trace!(
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"domctl fd={} assign_device domid={} sbdf={} flags={}",
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self.handle.as_raw_fd(),
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domid,
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sbdf,
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flags,
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);
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let mut domctl = DomCtl {
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cmd: XEN_DOMCTL_ASSIGN_DEVICE,
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interface_version: self.domctl_interface_version,
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domid,
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value: DomCtlValue {
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assign_device: AssignDevice {
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device: DOMCTL_DEV_PCI,
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flags,
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pci_assign_device: PciAssignDevice { sbdf, padding: 0 },
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},
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},
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};
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self.hypercall1(HYPERVISOR_DOMCTL, addr_of_mut!(domctl) as c_ulong)
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.await?;
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Ok(())
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}
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}
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@ -104,6 +104,7 @@ pub const XEN_DOMCTL_CDF_HAP: u32 = 1u32 << 1;
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pub const XEN_DOMCTL_CDF_S3_INTEGRITY: u32 = 1u32 << 2;
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pub const XEN_DOMCTL_CDF_OOS_OFF: u32 = 1u32 << 3;
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pub const XEN_DOMCTL_CDF_XS_DOMAIN: u32 = 1u32 << 4;
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pub const XEN_DOMCTL_CDF_IOMMU: u32 = 1u32 << 5;
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pub const XEN_X86_EMU_LAPIC: u32 = 1 << 0;
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pub const XEN_X86_EMU_HPET: u32 = 1 << 1;
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@ -239,6 +240,8 @@ pub union DomCtlValue {
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pub get_page_frame_info: GetPageFrameInfo3,
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pub ioport_permission: IoPortPermission,
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pub iomem_permission: IoMemPermission,
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pub irq_permission: IrqPermission,
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pub assign_device: AssignDevice,
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pub pad: [u8; 128],
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}
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@ -327,6 +330,14 @@ pub struct IoMemPermission {
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pub allow: u8,
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}
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#[repr(C)]
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#[derive(Copy, Clone, Debug)]
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pub struct IrqPermission {
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pub pirq: u32,
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pub allow: u8,
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pub pad: [u8; 3],
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}
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#[repr(C)]
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#[derive(Copy, Clone, Debug, Default)]
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#[cfg(target_arch = "x86_64")]
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@ -396,7 +407,8 @@ pub struct MultiCallEntry {
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}
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pub const XEN_MEM_POPULATE_PHYSMAP: u32 = 6;
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pub const XEN_MEM_MEMORY_MAP: u32 = 9;
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pub const XEN_MEM_MEMORY_MAP: u32 = 10;
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pub const XEN_MEM_SET_MEMORY_MAP: u32 = 13;
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pub const XEN_MEM_CLAIM_PAGES: u32 = 24;
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#[repr(C)]
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@ -406,6 +418,13 @@ pub struct MemoryMap {
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pub buffer: c_ulong,
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}
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#[repr(C)]
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#[derive(Copy, Clone, Debug)]
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pub struct ForeignMemoryMap {
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pub domid: u16,
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pub map: MemoryMap,
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}
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#[repr(C)]
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#[derive(Copy, Clone, Debug)]
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pub struct VcpuGuestContextFpuCtx {
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@ -600,3 +619,61 @@ pub struct EvtChnAllocUnbound {
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pub remote_dom: u16,
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pub port: u32,
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}
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#[cfg(target_arch = "x86_64")]
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#[repr(C, packed)]
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#[derive(Debug, Copy, Clone, Default)]
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pub struct E820Entry {
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pub addr: u64,
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pub size: u64,
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pub typ: u32,
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}
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#[cfg(target_arch = "x86_64")]
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pub const E820_MAX: u32 = 1024;
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#[cfg(target_arch = "x86_64")]
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pub const E820_RAM: u32 = 1;
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#[cfg(target_arch = "x86_64")]
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pub const E820_RESERVED: u32 = 2;
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#[cfg(target_arch = "x86_64")]
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pub const E820_ACPI: u32 = 3;
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#[cfg(target_arch = "x86_64")]
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pub const E820_NVS: u32 = 4;
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#[cfg(target_arch = "x86_64")]
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pub const E820_UNUSABLE: u32 = 5;
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pub const PHYSDEVOP_MAP_PIRQ: u64 = 13;
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#[repr(C)]
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#[derive(Default, Clone, Copy, Debug)]
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pub struct PhysdevMapPirq {
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pub domid: u16,
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pub typ: c_int,
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pub index: c_int,
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pub pirq: c_int,
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pub bus: c_int,
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pub devfn: c_int,
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pub entry_nr: u16,
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pub table_base: u64,
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}
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pub const DOMCTL_DEV_RDM_RELAXED: u32 = 1;
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pub const DOMCTL_DEV_PCI: u32 = 0;
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pub const DOMCTL_DEV_DT: u32 = 1;
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#[repr(C)]
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#[derive(Default, Clone, Copy, Debug)]
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pub struct PciAssignDevice {
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pub sbdf: u32,
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pub padding: u64,
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}
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#[repr(C)]
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#[derive(Default, Clone, Copy, Debug)]
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pub struct AssignDevice {
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pub device: u32,
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pub flags: u32,
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pub pci_assign_device: PciAssignDevice,
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}
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pub const DOMID_IO: u32 = 0x7FF1;
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@ -30,7 +30,10 @@ use std::path::PathBuf;
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use std::str::FromStr;
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use std::time::Duration;
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use uuid::Uuid;
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use xencall::sys::{CreateDomain, XEN_DOMCTL_CDF_HAP, XEN_DOMCTL_CDF_HVM_GUEST};
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use xencall::sys::{
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CreateDomain, DOMCTL_DEV_RDM_RELAXED, XEN_DOMCTL_CDF_HAP, XEN_DOMCTL_CDF_HVM_GUEST,
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XEN_DOMCTL_CDF_IOMMU,
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};
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use xencall::XenCall;
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use xenstore::{
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XsPermission, XsdClient, XsdInterface, XS_PERM_NONE, XS_PERM_READ, XS_PERM_READ_WRITE,
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@ -83,7 +86,7 @@ pub struct DomainEventChannel {
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pub name: String,
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}
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#[derive(Clone, Debug, Default)]
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#[derive(Clone, Debug, Default, Eq, PartialEq)]
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pub enum DomainPciRdmReservePolicy {
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Invalid,
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#[default]
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@ -151,12 +154,14 @@ impl XenClient {
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pub async fn create(&self, config: &DomainConfig) -> Result<CreatedDomain> {
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let mut domain = CreateDomain {
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max_vcpus: config.max_vcpus,
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..Default::default()
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};
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domain.max_vcpus = config.max_vcpus;
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if cfg!(target_arch = "aarch64") {
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domain.flags = XEN_DOMCTL_CDF_HVM_GUEST | XEN_DOMCTL_CDF_HAP;
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} else {
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domain.flags = XEN_DOMCTL_CDF_IOMMU;
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}
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let domid = self.call.create_domain(domain).await?;
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@ -724,6 +729,20 @@ impl XenClient {
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}
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}
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// backend.reset(&device.bdf).await?;
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self.call
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.assign_device(
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domid,
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device.bdf.encode(),
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if device.rdm_reserve_policy == DomainPciRdmReservePolicy::Relaxed {
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DOMCTL_DEV_RDM_RELAXED
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} else {
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0
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},
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)
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.await?;
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let id = 60;
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if index == 0 {
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@ -753,13 +772,16 @@ impl XenClient {
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}
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let backend_path = format!("{}/backend/{}/{}/{}", backend_dom_path, "pci", domid, id);
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self.store
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let transaction = self.store.transaction().await?;
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transaction
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.write_string(
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format!("{}/key-{}", backend_path, index),
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&device.bdf.to_string(),
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)
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.await?;
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self.store
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transaction
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.write_string(
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format!("{}/dev-{}", backend_path, index),
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&device.bdf.to_string(),
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@ -767,7 +789,7 @@ impl XenClient {
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.await?;
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if let Some(vdefn) = device.bdf.vdefn {
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self.store
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transaction
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.write_string(
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format!("{}/vdefn-{}", backend_path, index),
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&format!("{:#x}", vdefn),
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@ -789,10 +811,11 @@ impl XenClient {
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.collect::<Vec<_>>()
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.join(",");
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self.store
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transaction
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.write_string(format!("{}/opts-{}", backend_path, index), &options)
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.await?;
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transaction.commit().await?;
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Ok(())
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}
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@ -52,9 +52,22 @@ impl XenPciBackend {
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Ok(fs::try_exists(path).await?)
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}
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pub async fn read_irq(&self, bdf: &PciBdf) -> Result<Option<u32>> {
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let mut path: PathBuf = self.path.clone();
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path.push(bdf.to_string());
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path.push("irq");
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if !path.exists() {
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return Ok(None);
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}
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let content = fs::read_to_string(&path).await?;
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Ok(u32::from_str(content.trim()).ok())
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}
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pub async fn read_resources(&self, bdf: &PciBdf) -> Result<Vec<PciMemoryResource>> {
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let mut resources = Vec::new();
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let mut path = self.path.clone();
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let mut path: PathBuf = self.path.clone();
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path.push(bdf.to_string());
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path.push("resource");
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let content = fs::read_to_string(&path).await?;
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@ -112,6 +125,13 @@ impl XenPciBackend {
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}
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Ok(false)
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}
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pub async fn reset(&self, bdf: &PciBdf) -> Result<()> {
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let mut path: PathBuf = self.path.clone();
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path.push("do_flr");
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fs::write(&path, bdf.to_string()).await?;
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Ok(())
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}
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}
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#[derive(Debug, Clone, Copy, Eq, PartialEq, Hash)]
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@ -149,6 +169,14 @@ impl PciBdf {
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vdefn: self.vdefn,
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}
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}
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pub fn encode(&self) -> u32 {
|
||||
let mut value = self.domain.unwrap_or(0) << 16u32;
|
||||
value |= ((self.bus & 0xff) << 8u32) as u32;
|
||||
value |= ((self.device & 0x1f) << 3u32) as u32;
|
||||
value |= (self.function & 0x7) as u32;
|
||||
value
|
||||
}
|
||||
}
|
||||
|
||||
impl FromStr for PciBdf {
|
||||
|
||||
@ -11,7 +11,9 @@ use slice_copy::copy;
|
||||
use std::cmp::{max, min};
|
||||
use std::mem::size_of;
|
||||
use std::slice;
|
||||
use xencall::sys::{VcpuGuestContext, MMUEXT_PIN_L4_TABLE};
|
||||
use xencall::sys::{
|
||||
E820Entry, VcpuGuestContext, E820_MAX, E820_RAM, E820_UNUSABLE, MMUEXT_PIN_L4_TABLE,
|
||||
};
|
||||
|
||||
pub const X86_PAGE_SHIFT: u64 = 12;
|
||||
pub const X86_PAGE_SIZE: u64 = 1 << X86_PAGE_SHIFT;
|
||||
@ -273,6 +275,154 @@ impl X86BootSetup {
|
||||
self.table.mappings[m] = map;
|
||||
Ok(m)
|
||||
}
|
||||
|
||||
fn e820_sanitize(
|
||||
&self,
|
||||
mut source: Vec<E820Entry>,
|
||||
map_limit_kb: u64,
|
||||
balloon_kb: u64,
|
||||
) -> Result<Vec<E820Entry>> {
|
||||
let mut e820 = vec![E820Entry::default(); E820_MAX as usize];
|
||||
|
||||
for entry in &mut source {
|
||||
if entry.addr > 0x100000 {
|
||||
continue;
|
||||
}
|
||||
|
||||
// entries under 1MB should be removed.
|
||||
entry.typ = 0;
|
||||
entry.size = 0;
|
||||
entry.addr = u64::MAX;
|
||||
}
|
||||
|
||||
let mut lowest = u64::MAX;
|
||||
let mut highest = 0;
|
||||
|
||||
for entry in &source {
|
||||
if entry.typ == E820_RAM || entry.typ == E820_UNUSABLE || entry.typ == 0 {
|
||||
continue;
|
||||
}
|
||||
|
||||
lowest = if entry.addr < lowest {
|
||||
entry.addr
|
||||
} else {
|
||||
lowest
|
||||
};
|
||||
|
||||
highest = if entry.addr + entry.size > highest {
|
||||
entry.addr + entry.size
|
||||
} else {
|
||||
highest
|
||||
}
|
||||
}
|
||||
|
||||
let start_kb = if lowest > 1024 { lowest >> 10 } else { 0 };
|
||||
|
||||
let mut idx: usize = 0;
|
||||
|
||||
e820[idx].addr = 0;
|
||||
e820[idx].size = map_limit_kb << 10;
|
||||
e820[idx].typ = E820_RAM;
|
||||
|
||||
let mut delta_kb = 0u64;
|
||||
|
||||
if start_kb > 0 && map_limit_kb > start_kb {
|
||||
delta_kb = map_limit_kb - start_kb;
|
||||
if delta_kb > 0 {
|
||||
e820[idx].size -= delta_kb << 10;
|
||||
}
|
||||
}
|
||||
|
||||
let ram_end = source[0].addr + source[0].size;
|
||||
idx += 1;
|
||||
|
||||
for src in &mut source {
|
||||
let end = src.addr + src.size;
|
||||
if src.typ == E820_UNUSABLE || end < ram_end {
|
||||
src.typ = 0;
|
||||
continue;
|
||||
}
|
||||
|
||||
if src.typ != E820_RAM {
|
||||
continue;
|
||||
}
|
||||
|
||||
if src.addr >= (1 << 32) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if src.addr < ram_end {
|
||||
let delta = ram_end - src.addr;
|
||||
src.typ = E820_UNUSABLE;
|
||||
|
||||
if src.size < delta {
|
||||
src.typ = 0;
|
||||
} else {
|
||||
src.size -= delta;
|
||||
src.addr = ram_end;
|
||||
}
|
||||
|
||||
if src.addr + src.size != end {
|
||||
src.typ = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if end > ram_end {
|
||||
src.typ = E820_UNUSABLE;
|
||||
}
|
||||
}
|
||||
|
||||
if lowest > ram_end {
|
||||
let mut add_unusable = true;
|
||||
|
||||
for src in &mut source {
|
||||
if !add_unusable {
|
||||
break;
|
||||
}
|
||||
|
||||
if src.typ != E820_UNUSABLE {
|
||||
continue;
|
||||
}
|
||||
|
||||
if ram_end != src.addr {
|
||||
continue;
|
||||
}
|
||||
|
||||
if lowest != src.addr + src.size {
|
||||
src.size = lowest - src.addr;
|
||||
}
|
||||
add_unusable = false;
|
||||
}
|
||||
|
||||
if add_unusable {
|
||||
e820[1].typ = E820_UNUSABLE;
|
||||
e820[1].addr = ram_end;
|
||||
e820[1].size = lowest - ram_end;
|
||||
}
|
||||
}
|
||||
|
||||
for src in &source {
|
||||
if src.typ == E820_RAM || src.typ == 0 {
|
||||
continue;
|
||||
}
|
||||
|
||||
e820[idx].typ = src.typ;
|
||||
e820[idx].addr = src.addr;
|
||||
e820[idx].size = src.size;
|
||||
idx += 1;
|
||||
}
|
||||
|
||||
if balloon_kb > 0 || delta_kb > 0 {
|
||||
e820[idx].typ = E820_RAM;
|
||||
e820[idx].addr = if (1u64 << 32u64) > highest {
|
||||
1u64 << 32u64
|
||||
} else {
|
||||
highest
|
||||
};
|
||||
e820[idx].size = (delta_kb << 10) + (balloon_kb << 10);
|
||||
}
|
||||
Ok(e820)
|
||||
}
|
||||
}
|
||||
|
||||
#[async_trait::async_trait]
|
||||
@ -615,6 +765,13 @@ impl ArchBootSetup for X86BootSetup {
|
||||
let pg_mfn = setup.phys.p2m[pg_pfn as usize];
|
||||
setup.phys.unmap(pg_pfn)?;
|
||||
setup.phys.unmap(p2m_segment.pfn)?;
|
||||
|
||||
let map = setup.call.get_memory_map(E820_MAX).await?;
|
||||
let mem_mb = setup.total_pages >> (20 - self.page_shift());
|
||||
let mem_kb = mem_mb * 1024;
|
||||
let e820 = self.e820_sanitize(map, mem_kb, 0)?;
|
||||
setup.call.set_memory_map(setup.domid, e820).await?;
|
||||
|
||||
setup
|
||||
.call
|
||||
.mmuext(setup.domid, MMUEXT_PIN_L4_TABLE, pg_mfn, 0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user